1. Field of the Invention
The present invention relates to a system on chip (SOC), and more particularly to a method and a chip adapted for expanding pins of the chip.
2. Description of Related Art
With the development of system on chip (SOC), integrated circuits can perform more functions and are more sophisticated. In order to integrate chips with different functions in a single chip, I/O pins of the chip are also gradually increased. The packaging cost of integrated circuits with a large number of pins is high. Therefore, reducing the packing costs for integrated circuits is an important object in this industry.
To overcome the problem resulting from the integration of multiple chips, one approach is to expand the number of pins. Another approach is to use multiple-functional pins via a specific interface to reduce the number of pins. For example, Intel Corp. disclosed a low pin count (LPC) interface, which substantially reduces the number of pins of flash memory interface. This technique is widely adopted in this industry. Although this technique is capable of reducing the number of pins of some specific interfaces, however, this technique does not resolve the problem that new interfaces require additional pins. If additional pins for a new interface are required, still packaging of integrated circuits with high pin count is required, and therefore increase in the packaging costs is inevitable.